A flash memory is typically configured by an array of multiplicity of memory cells aligned in the word line direction and the bit line direction. A memory cell is configured by a stacked gate structure in which a floating gate electrode, interelectrode insulating film, and control gate electrode are stacked in the listed sequence. As flash memory increases its storage capacity through densification, features within the memory cell are packed in tighter dimensions. Dimensions typically affected by the densification are widths of floating gate electrodes and element isolation trenches.
As the memory cells become smaller, relatively higher electric field is applied to the floating gate electrode through the interelectrode insulating film during programming. This is because downscaling of a memory cell often results in a floating gate electrode with a sharp tip. Because electric field tends to concentrate at the tips, edges, and corners, the downscaled floating gate having relatively larger percentage of such high electric field regions are subjected to larger amount of high electric field leakage current which prevents the memory cell from being programmed to the desired threshold.
The interelectrode insulating film is often configured by an ONO structure in which a silicon nitride film is interposed between the top silicon oxide film and the bottom silicon oxide film. The silicon nitride film in the middle layer of the stack traps electrons that positively affect the programming properties of the cell. As the element isolation trenches become narrower, the electrons trapped in the silicon nitride film of the interelectrode insulating film formed above the element isolation insulating film cause a shift in the programming threshold of the adjacent cell, which typically causes programming errors.